1. Field
Example embodiments are directed to semiconductor packages, and more particularly, to semiconductor packages with improved joint reliability.
2. Description of the Related Art
Semiconductor packages connect an input/output terminal of a chip to an external device, and simultaneously protect the chip. As semiconductor devices are manufactured to have smaller sizes and higher performances, inexpensive semiconductor packages with improved reliability are required. To meet this need, flip chip packages, wafer level packages, and wafer level stack packages, which do not require wire bonding, have been developed.
In a wafer level package, semiconductor chips are assembled or packaged in a single wafer operation prior to separating the chips, unlike conventional lead frame packages. Therefore, the packaging processes may be performed simultaneously, allowing the assembly operation for all semiconductor chips disposed on a wafer to be finished at the same time. As a result, the manufacturing cost of each semiconductor device may be reduced, while allowing the functions of the semiconductor package and chip to be completely integrated. In addition, the size of a semiconductor package may be reduced to almost match the size of a semiconductor chip, a reduction over other packaging technologies (e.g. lead frame packaging).
Further, a conventional lead frame package uses leads as external connection terminals, with the leads being one-dimensionally disposed around the edge of a semiconductor chip. In contrast, a wafer level package allows solder balls, disposed throughout the lower surface of the package, to function as external connection terminals. Thus, external connection terminals may be effectively arranged in the wafer level package.
However, in wafer level packaging, because a semiconductor chip is directly connected to the substrate of a printed circuit board through solder balls, cracks are generated at solder joints due to a mismatch in the coefficient of thermal expansion (CTE). This mismatch causes pressure and tensile stress between the substrate and the solder ball, generating cracks at the solder ball joints in response to temperature changes, for example, during thermal processing.